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7.3
Data Interface
Normal operation is entered by applying correct LRFS, BCLK and SDIN waveforms to the serial
To avoid noise at the output, the reset state is maintained until proper synchronization is
achieved in the serial interface.
The data interface allows three different data transfer modes. See Figure 7-4 , Figure 7-5 and
Figure 7-4.
BCLK
LRFS
20-bit I2S Justified Mode
SDIN
R1
R0
L(N-1)
L(N-2)
L(N-3)
...
L2
L1
L0
R(N-1)
R(N-2)
R(N-3)
...
R2
R1
R0
Figure 7-5.
BCLK
LRFS
20-bit MSB Justified Mode
SDIN
R0
L(N-1)
L(N-2)
L(N-3)
...
L2
L1
L0
R(N-1)
R(N-2)
R(N-3)
...
R2
R1
R0
L(N-1)
Figure 7-6.
BCLK
LRFS
20-bit LSB Justified Mode
SDIN
R0
L(N-1)
L(N-2)
...
L1
L0
R(N-1)
R(N-2)
...
R1
R0
L(N-1)
The selection between modes is done using the DINTSEL<1:0> signal.
DINTSEL <1:0>
00
01
1x
Format
I2S Justified
MSB Justified
LSB Justified
The data interface always works in slave mode. This means that the LRFS and the BCLK sig-
nals are provided by the host controller. In order to achieve proper operation, the LRFS and the
BCLK signals must be synchronous with the MCLK master clock signal and their frequency rela-
tionship must reflect the selected data mode. For example, if the data mode selected is the 20-
bit MSB Justified, then the BCLK frequency must be 40 times higher than the LRFS frequency.
10
AT73C213
2744B–PMAAC–11-Apr-08
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